For signals with very high bandwidth, analog filtering is often more economical than digital filtering. Even where costs are less important, there are still cases where analog filtering is the only viable method for performing signal-processing functions.
Examples of high-bandwidth signals that may require analog filtering include disk drive read channels, radio communication channels, wireline communication channels and fiber-optic communication channels. The types of processing that must be performed on these signals include channel response equalization and channel phase compensation.
Three broad categories encompass several prior art analog filters. These categories may be distinguished based on the type of method each uses to create signal delays during the filtering process.
In FIG. 1, a representative continuous-time integrator based filter is shown and generally designated 100. Filter 100, and other filters included in this category generate signal delays using a series of integrators 102 (that are individually labeled in FIG. 1 as 102a-102n). Each integrator 102 is typically implemented as an inductor or capacitor. The primary disadvantage of this type of filter is that it cannot compensate for distributed or noncausal errors in the channel.
FIG. 2 shows an example of a continuous-time transmission-line based filter 200. Unlike Filter 100, Filter 200 has a finite impulse response (FIR) (i.e., the filter is non-recursive and does not process feedback). For Filter 200, signal delays are generated by a plurality of transmission lines 202. Each transmission line 202C is typically implemented as a stripline. The primary disadvantage of the type of filter is that the transmission lines are physically large. As a result, it is difficult to implement circuits of this type in integrated-circuit technologies.
FIG. 3 shows an example of a discrete-time analog filter 300. In this type of filter, delays are generated by a series of sample-and-hold circuits 302. Filter 300 has a finite impulse response (FIR) and is further described in U.S. Pat. No. 4,316,258, issued to Berger, et. al., for an invention entitled xe2x80x9cDigitally programmable filter using electrical charge transferxe2x80x9d.
Operation of filter 300 can be described as follows: The first sample and hold circuit 302a samples the input signal x(t) at uniformly spaced times 0, T, 2T, . . . and generating samples x(0), x(T), x(2T), . . . The second sample and hold circuit 302b samples the output of sample and hold circuit 302a before sample and hold circuit 302a acquires a new sample (e.g., between times O and T), thus obtaining the previous sample value (e.g., x(o)). Therefore, at time t=kT, the output of circuit 302a is x(kT) whereas the output of circuit 302b is x((kxe2x88x921)T). Each sample and hold circuit 302I behaves in this manner relative to its preceding circuit. The output of each sample and hold circuit 302n at time t=kT is therefore as shown in FIG. 3. To perform the filtering, each of the output samples Sn from each circuit 302n is multiplied by a coefficient Cn, and the resulting products are then added together. The result is a filtered version of the sampled input signal with the filter transfer function given by:
H(z)=C0+C1zxe2x88x921+C2zxe2x88x922+ . . .
where z is the unit delay operator. The filter architecture of FIG. 3 suffers from several significant disadvantages. First each sample and hold circuit 302n samples during the hold phase of the preceding sample and hold circuit 302 in the pipeline, thus requiring two track-and-holds for each filter tap. Second, noise, offset, and nonlinearity errors accumulate as the signal propagates along the chain of sample and hold circuits 302. See S. Kiriaki, T. L. Viswanathan, G. Feygin, B. Stazewski, R. Pierson, B. Krenik, M. de Wit, K. Nagaraj, xe2x80x9cA 160-MHz Analog Equalizer for Magnetic Disk Read Channelsxe2x80x9d, IEEE Journal of Solid State Circuits, vol. 32, no. 11, November 1997, pp. 1839-1850.
An architecture that does not have these two disadvantages is illustrated by filter 400 of FIG. 4. Filter 400 has a finite impulse response. Filter 400 includes a series of n+1 track and hold circuits 402, a crosspoint switch matrix 404, a series of n multipliers 406 and an adder 408.
Track and hold circuits 402 have two operational states. During track mode, track and hold 402 transfers their input to their outputs with a gain of one. During hold mode, track and hold circuits 402 outputs their last transferred values. This differs from sample and hold circuits, which output sample value without having a tracking (transfer or pass-through) mode.
Crosspoint switch matrix 404 has n+1 inputs and n outputs. Each track and hold circuit 402 is connected to one of these inputs. Each of these outputs is connected to a respective multiplier 406i. The outputs of multipliers 406 are connected to the n inputs of an adder 408. Crosspoint 404 switch matrix contains a switch connecting each of its (n+1) inputs to each of its n outputs, with one switch per output being closed at any given time. This allows crosspoint switch matrix 404 to select any set of n inputs from among the n+1 inputs and pass that set of n inputs to its n outputs.
A control circuit (not shown) clocks and controls the operation of filter 400. During each clock period, the control circuit causes one track and hold circuit 402 (known as the active track and hold circuit 402) to track the input signal. This means that the active track and hold 402 transfers its input (the input signal) to its output with a gain of one. The control circuit causes the remaining track and hold circuits 402 to remain in hold mode. Each of these track and hold circuits 402 outputs its last transferred value of the input signal. During subsequent clock periods, the control circuit causes the active track and hold circuit 402 to rotate among the series of track and hold circuits 402.
At time t=kT, valid samples will be present in the inactive track and holds, the samples representing x((kxe2x88x921)T), x((kxe2x88x922)T), . . . x((kxe2x88x92n)T). The location of the samples at the inputs to matrix 404 will be different at each instant of time. However, because of the rotating nature of the sampling, e.g., the control circuit configures the crosspoint switch matrix 404 to map the inputs from the appropriate track and hold circuits 402 (i.e., the track and hold circuits 402 having valid sample values) to respective multipliers 406. The multiplied samples are forwarded to adder 408. Adder 408 sums the multiplied samples to form a filtered output signal y[k].
Filter 400 suffers from several disadvantages. First, the number of switches in crosspoint switch matrix 404 grows roughly as the square of the number of taps:
Nswitch=n(n+1).
The large number of switches results in a large parasitic capacitance at each of the input and output terminals of crosspoint switch matrix 404. This limits the speed of operation of the circuit. Second, the sampled signal must traverse the entire signal path, including crosspoint switch matrix 404, multipliers 406 and adder 408, within one clock cycle. For systems with high sampling rates (typically above 1-5 GHz), certain integrated circuit technology is not fast enough to perform all the processing with sufficient accuracy within the sample period. As a result, filters using this architecture may suffer from a bottleneck in terms of sampling rate and accuracy.
Additional description of Filter 400 may be found in: 1) S. Kiriaki, T. L. Viswanathan, G. Feygin, B. Stazewski, R. Pierson, B. Krenik, M. de Wit, K. Nagaraj, xe2x80x9cA 160-MHz Analog Equalizer for Magnetic Disk Read Channelsxe2x80x9d, IEEE Journal of Solid State Circuits, vol. 32, no. 11, November 1997, pp. 1839-1850. 2) Kiriaki, et al., xe2x80x9cFIR filter architecturexe2x80x9d, U.S. Pat. No. 6,035,320, Mar. 7, 2000. 3) Carley, xe2x80x9cSample and hold circuit and finite impulse response filter constructed therefromxe2x80x9d, U.S. Pat. No. 5,414,311, May 9, 1995.
For these and other reasons, a need exists for improved methods for analog filtering. This need is present in cases where bandwidth requirements are high and error rates are required to be low.
The present invention relates to an improved filter architecture that calculates two or more (e.g., m greater than 1) samples of the filter output in parallel. The parallel outputs can be used in parallel, typically as the inputs to a series of parallel analog to digital converters.
In one embodiment, at least m track and hold circuits are active at any time. Specifically, the filter comprises n+2mxe2x88x921 track and holds, of which m are active and n+mxe2x88x921 are inactive at any given time. The m active track and holds transition from the track phase to the hold phase in a staggered fashion. This results in the m active track and holds sampling the input at times x(kT), x((kxe2x88x921)T), . . . x((kxe2x88x92m+1)T). The role of the m active track and holds is rotated among the available track and holds in a group fashion. First, one group of track and holds T1 . . . Tm are active, then another group of track and holds Tm+1 . . . T2m are active, and so forth until track and holds Tn+mxe2x88x921 . . . Tn+2mxe2x88x921 are active, after which T1 . . . Tm become active again. Because the xe2x80x9cactivexe2x80x9d role of each group of track and holds changes only every mth sample period, the outputs of the inactive track and holds remain constant for an interval of m sample periods.
During this interval of m sample periods, m samples of the filter output are calculated in parallel. A switch matrix is used to place the input samples obtained by the track and holds in the proper order for the filtering operations. The output of the switch matrix is a series of samples x((kxe2x88x921)T) . . . (x(kxe2x88x92nxe2x88x92m+1)T. Because the order within each group of m sample and holds remains constant, the switch matrix only needs to select from among the (nxe2x88x921)/m+2 groups. This reduces the size of the switch matrix by a factor of m.
Specifically, the size of the crosspoint switch matrix is reduced from n (n+1) switches to approximately
Nswitch=(n+mxe2x88x921)(n+2mxe2x88x921)/m
and the time allotted for the signal to traverse the crosspoint switch matrix, the multipliers and the adder is increased from T to mT.
The ordered input samples provided by the matrix are then multiplied by the corresponding filter coefficients to produce the first filtered output y[k]
xe2x80x83y[k]=C0x((kxe2x88x921)T)+C1x((kxe2x88x922)T)+C2x((kxe2x88x923)T)+ . . . +Cnxe2x88x921x((kxe2x88x92n)T)
The second filter output is generated by applying the same filter coefficients to a shifted version of the series of input samples
y[kxe2x88x921]=C0x((kxe2x88x922)T)+C1x((kxe2x88x923)T)+C2x((kxe2x88x924)T)+ . . . +Cnxe2x88x921x((kxe2x88x92nxe2x88x921)T)
and subsequent filter outputs are generated in an analogous fashion.
If (nxe2x88x921)/m is not an integer, then the architecture can still be implemented, but the number of sample and holds increases to m*ceil((nxe2x88x921)/m)+2m where ceil(u) denotes the smallest integer greater than or equal to u.
To allow for a longer tracking period, additional track and holds can be added in groups of m. In this case, the number of track and holds active at any given time is p+m, where p is the number of extra track and holds added.